• Decommutation of Mil-Std 1553B Data from EA6B or IRIG Telemetry Formats

      Devlin, Steve; Aydin Monitor Systems (International Foundation for Telemetering, 1988-10)
      With the acceptance of Mil-Std-1553B by vehicle and weapons industries a wealth of new information is available for vehicle testing. In the past, selected data was extracted and included in a standard PCM telemetry stream. But only the selected data was made available. In EA6B and in the proposed IRIG Standard, multiple Mil-Std-1553B data busses are combined with identifying control bits in a single PCM telemetry stream. All of the information traveling each bus is available to the ground station. These formats share a number of features. One is that for each Bus the Mil-Std-1553B word appears in the same order in the telemetry stream. Another is that individual data words do not depend on their position in the telemetry stream for identification, but they do depend on the control information associated with the current message to give meaning to the data words. An efficient approach is outlined for identifying, selecting and routing individual measurements, messages, and/or all Mil-Std-1553B bus information to processes and I/O devices in a data flow environment.
    • Off-Loading the Host Computer Through Flexible DMA Interface

      Nicolo, Stephen J.; Aydin Monitor Systems (International Foundation for Telemetering, 1988-10)
      As data rates and system throughput requirements continue to increase, more and more attention must be given to ways of off-loading the host computer by shifting tasks to the front-end preprocessing subsystem. In addition to some of the more common tasks like data compression and EU conversion already performed in the front end, there is the time consuming task of organizing telemetry data. Once relieved from this secondary task the host can solely attend to its primary task of application processing. This paper describes an intelligent DMA interface (CPI007) which permits the automatic building of various types of array buffers in the host computer. This flexible high-speed device uses an EPROM based, bit slice microengine utilizing parameters stored in its operational store RAM during setup to build the array buffers. The interface is implemented on a single module in the front-end preprocessing subsystem and was developed for those mainframe computers that can be configured to accept address/data inputs for DMA to system memory (e.g. Gould Sel, DEC). With this type of architecture, algorithms may easily be written to accommodate a wide variety of data organization and transfer requirements. Along with the technical description of this device, actual data array buffering problems and solutions will also be addressed in this paper.
    • Practical Decom List Switching

      Devlin, Steve; Aydin Monitor Systems (International Foundation for Telemetering, 1988-10)
      With more complex vehicle designs, the frequency and number of measurements contained in telemetry data streams has dramatically increased. One way of improving the use of bandwidth is to change the sample rate, quantity, or type of measurements dynamically. A telemetry front end must be programmable to handle different formats. In a front end that decommutates and routes measurements, a decom list is a control program, which defines the location, size, orientation, and identity of the measurements. To deal with dynamic format changes, a telemetry front end must be able to switch between decom lists. A practical approach to decom list switching must address the needs of error avoidance, packet switching, and the location of switching keys in any portion of the format. Switching between formats should not be restricted to a preprogrammed sequence, but should allow multiple destinations from a particular decom list. A practical and flexible implementation of decom list switching is detailed along with an explanation of how this implementation solves a variety of decommutation problems.
    • Telemetry Data Processing: A Modular, Expandable Approach

      Devlin, Steve; Aydin Monitor Systems (International Foundation for Telemetering, 1988-10)
      The growing complexity of missle, aircraft, and space vehicle systems, along with the advent of fly-by-wire and ultra-high performance unstable airframe technology has created an exploding demand for real time processing power. Recent VLSI developements have allowed addressing these needs in the design of a multi-processor subsystem supplying 10 MIPS and 5 MFLOPS per processor. To provide up to 70 MIPS a Digital Signal Processing subsystem may be configured with up to 7 Processors. Multiple subsystems may be employed in a data processing system to give the user virtually unlimited processing power. Within the DSP module, communication between cards is over a high speed, arbitrated Private Data bus. This prevents the saturation of the system bus with intermediate results, and allows a multiple processor configuration to make full use of each processor. Design goals for a single processor included executing number system conversions, data compression algorithms and 1st order polynomials in under 2 microseconds, and 5th order polynomials in under 4 microseconds. The processor design meets or exceeds all of these goals. Recently upgraded VLSI is available, and makes possible a performance enhancement to 11 MIPS and 9 MFLOPS per processor with reduced power consumption. Design tradeoffs and example applications are presented.