Browsing International Telemetering Conference Proceedings, Volume 24 (1988) by Subjects
Now showing items 1-2 of 2
Decommutation of Mil-Std 1553B Data from EA6B or IRIG Telemetry FormatsWith the acceptance of Mil-Std-1553B by vehicle and weapons industries a wealth of new information is available for vehicle testing. In the past, selected data was extracted and included in a standard PCM telemetry stream. But only the selected data was made available. In EA6B and in the proposed IRIG Standard, multiple Mil-Std-1553B data busses are combined with identifying control bits in a single PCM telemetry stream. All of the information traveling each bus is available to the ground station. These formats share a number of features. One is that for each Bus the Mil-Std-1553B word appears in the same order in the telemetry stream. Another is that individual data words do not depend on their position in the telemetry stream for identification, but they do depend on the control information associated with the current message to give meaning to the data words. An efficient approach is outlined for identifying, selecting and routing individual measurements, messages, and/or all Mil-Std-1553B bus information to processes and I/O devices in a data flow environment.
Telemetry Data Processing: A Modular, Expandable ApproachThe growing complexity of missle, aircraft, and space vehicle systems, along with the advent of fly-by-wire and ultra-high performance unstable airframe technology has created an exploding demand for real time processing power. Recent VLSI developements have allowed addressing these needs in the design of a multi-processor subsystem supplying 10 MIPS and 5 MFLOPS per processor. To provide up to 70 MIPS a Digital Signal Processing subsystem may be configured with up to 7 Processors. Multiple subsystems may be employed in a data processing system to give the user virtually unlimited processing power. Within the DSP module, communication between cards is over a high speed, arbitrated Private Data bus. This prevents the saturation of the system bus with intermediate results, and allows a multiple processor configuration to make full use of each processor. Design goals for a single processor included executing number system conversions, data compression algorithms and 1st order polynomials in under 2 microseconds, and 5th order polynomials in under 4 microseconds. The processor design meets or exceeds all of these goals. Recently upgraded VLSI is available, and makes possible a performance enhancement to 11 MIPS and 9 MFLOPS per processor with reduced power consumption. Design tradeoffs and example applications are presented.