• Field Programmable Gate Array Based Miniaturised Central Controller for a Decentralised Base-Band Telemetry System for Satellite Launch Vehicles

      Krishnakumar, M.; Sreelal, S.; Narayana, T. V.; Anguswamy, P.; Singh, U. S.; Indian Space Research Organisation (International Foundation for Telemetering, 1995-11)
      The Central Control Unit (CCU) for a decentralised on-board base-band telemetry system is designed for use in launch vehicle missions of the Indian Space Research Organisation (ISRO). This new design is a highly improved and miniaturised version of an earlier design. The major design highlights are as follows: usage of CMOS Field Programmable Gate Array (FPGA) devices in place of LS TTL devices, high level user programmability of TM format using EEPROMs, usage of high density memory for on-board data storage and delayed data transmission, HMC based pre-modulation filter and final output driver etc. The entire system is realised on a single 6 layer MLB and is packaged on a stackable modular frame. This design has resulted in a 1:4 reduction in weight, 1:4 reduction in volume, 1:5 reduction in power consumption and 1:3 reduction in height in addition to drastic reduction of part diversity and solder joints and thus greatly increased reliability. This paper discusses the design approach, implementation details, tools used, simulations carried out and the results of detailed qualification tests done on the realised qualification model.
    • FIELD PROGRAMMABLE GATE ARRAY BASED MINIATURISED REMOTE UNIT FOR A DECENTRALISED BASE-BAND TELEMETRY SYSTEM FOR SATELLITE LAUNCH VEHICLES

      M., Krishnakumar; G., Padma; S., Sreelal; V., Narayana T.; P., Anguswamy; S., Singh U.; Indian Space Research Organisation (International Foundation for Telemetering, 1995-11)
      The Remote Unit (RU) for a decentralised on-board base-band telemetry system is designed for use in launch vehicle missions of the Indian Space Research Organisation (ISRO). This new design is a highly improved and miniaturised version of an earlier design. The major design highlights are as follows. Usage of CMOS Field Programmable Gate Array (FPGA) technology in place of LS TTL devices, the ability to acquire various types of data like high level single ended or differential analog, bi-level events and two channels of high speed asynchronous serial data from On-Board Computers (OBCs), usage of HMC technology for the reduction of discrete parts etc. The entire system is realised on a single 6 layer MLB and is packaged on a stackable modular frame. This paper discusses the design approach, tools used, simulations carried out, implementation details and the results of detailed qualification tests done on the realised qualification model.