Browsing International Telemetering Conference Proceedings, Volume 31 (1995) by Subjects
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LOW COST SUBMINIATURE TELEMETRY SPREAD SPECTRUM TECHNOLOGY DEMONSTRATION/VALIDATIONEglin Air Force Base (AFB) plans to demonstrate subminiature telemetry (SMT) spread spectrum technology, via an upgraded prototype SMT system, to validate its cost-effectiveness for both Department of Defense (DoD) and commercial use. The goal is to develop new and/or modify current SMT instrumentation using existing production methods to provide increased capabilities at lower costs and reduced size. The transmitter is to require less than 2 cubic inches of space and have a cost goal of $500/unit "in quantity." The cost goal of a ground-based, 24-channel capable ground receiver is $4000/unit "in quantity". The SMT project as well as its schedule, flight and ground demonstrations, validation criteria and goals, and various benefits are discussed.
Shrinking the Cost of Telemetry Frame SynchronizationTo support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) targeted to dramatically lower the cost of telemetry frame synchronization. This single VLSI device, known as the Parallel Integrated Frame Synchronizer (PIFS) chip, integrates most of the functionality contained in high density 9U VME card frame synchronizer subsystems currently in use. In 1987, a first generation 20 Mbps VMEBus frame synchronizer based on 2.0 micron CMOS VLSI technology was developed by Data Systems Technology Division. In 1990, this subsystem architecture was recast using 0.8 micron ECL & GaAs VLSI to achieve 300 Mbps performance. The PIFS chip, based on 0.7 micron CMOS technology, will provide a superset of the current VMEBus subsystem functions at rates up to 500 Mbps at approximately one-tenth current replication costs. Functions performed by this third generation device include true and inverted 64 bit marker correlation with programmable error tolerances, programmable frame length and marker patterns, programmable search-check-lock-flywheel acquisition strategy, slip detection, and CRC error detection. Acquired frames can optionally be annotated with quality trailer and time stamp. A comprehensive set of cumulative accounting registers are provided on-chip for data quality monitoring. Prototypes of the PIFS chip are expected in October 1995. This paper will describe the architecture and implementation of this new low-cost high functionality device.
A VERY LOW COST 150 MBPS DESKTOP CCSDS GATEWAYThe wide use of standard packet telemetry protocols based on the Consultative Committee for Space Data Systems (CCSDS) recommendations in future space science missions has created a large demand for low-cost ground CCSDS processing systems. Some of the National Aeronautics and Space Administration (NASA) missions using CCSDS telemetry include Small Explorer, Earth Observing System (EOS), Space Station, and Advanced Composite Explorer. For each mission, ground telemetry systems are typically used in a variety of applications including spacecraft development facilities, mission control centers, science data processing sites, tracking stations, launch support equipment, and compatibility test systems. The future deployment of EOS spacecraft allowing direct broadcast of data to science users will further increase demand for such systems. For the last ten years, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center (GSFC) has been applying state-of-the-art commercial Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) technology to further reduce the cost of ground telemetry data systems. As a continuation of this effort, a new desktop CCSDS processing system is being prototyped that offers up to 150 Mbps performance at a replication cost of less than $20K. This system acts as a gateway that captures and processes CCSDS telemetry streams and delivers them to users over standard commercial network interfaces. This paper describes the development of this prototype system based on the Peripheral Component Interconnect (PCI) bus and 0.6 micron complementary metal oxide semiconductor (CMOS) ASIC technology. The system performs frame synchronization, bit transition density decoding, cyclic redundancy code (CRC) error checking, Reed-Solomon decoding, virtual channel sorting/filtering, packet extraction, and quality annotation and accounting at data rates up to and beyond 150 Mbps.