DESIGN OF A HIGH DYNAMIC GPS RECEIVER

Abstract

High dynamic and multi-channel digital GPS receiver can handle the signals with high dynamic range, low S/N ratio and refresh data quickly. A hardware design of high dynamic GPS digital receiver is given. Based on analysis of the effect that high dynamic movement makes on the receiving signals, a scheme of fast-acquisition high dynamic GPS receiver is presented. Exact reckoning of the orbit parameters and the satellite clock parameters are integrated with appropriate algorithms. A DDLL is used to precisely estimate the C/A code delay, a CPAFC loop and a Costas loop to precisely estimate the carrier frequency and phase. The DDLL is assisted with carrier phase. The experimental results show that the receiver meets the design request.