DIGITALLY IMPLEMENTED CLOCK ACQUISITION LOOPS FOR LOW SNR DATA SIGNALS

Abstract

The development of powerful error correction codes for binary data channels has generated a requirement for high performance clock acquisition loops. These loops must provide clean estimates of the data clock at very low data SNR in order to prevent dissipation of the coding gain through noise in the data recovery timing. The key element in high performance clock loops is the method of extracting clock information from the received data stream. Three loops are described which illustrate several extraction concepts and which can be used as design guides. The first loop extracts clock information by use of the function D(t)•D(t+ T/2). The extractor is implemented almost entirely with digital logic elements and is very compact. The third loop is extremely efficient due to the use of a time window which is open for only a short time around the transitions of the data. Its implementation is heavily analog. The second loop is a hybrid of the first and the third falls between them in both performance and complexity. Performance curves are presented for the three loops in terms of data SNR degradation as a function of data SNR and loop bandwidth. Experimental data is presented for the first loop.