Show simple item record

dc.contributor.authorHoltzman, Melinda
dc.contributor.authorJohnson, Bruce
dc.contributor.authorLautzenhiser, Lloyd
dc.date.accessioned2016-04-15T22:21:19Zen
dc.date.available2016-04-15T22:21:19Zen
dc.date.issued2003-10en
dc.identifier.issn0884-5123en
dc.identifier.issn0074-9079en
dc.identifier.urihttp://hdl.handle.net/10150/605595en
dc.descriptionInternational Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevadaen_US
dc.description.abstractPhase-locked loop (PLL) frequency synthesizers used for high-speed data transmission must rapidly hop and lock to new frequencies. The fundamental problem is that the settling time depends inversely on the loop bandwidth, and increasing the bandwidth causes unwanted noise interference and stability problems for the circuit. We demonstrate the feasibility of replacing the analog integrator in the PLL with a digital integrator. This circuit has advantages of increased hopping speed, ability to compensate for temperature drift and system stability. PLL lock-in was demonstrated in a prototype circuit designed and built with both discrete components and with a programmable logic device.
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.language.isoen_USen
dc.publisherInternational Foundation for Telemeteringen
dc.relation.urlhttp://www.telemetry.org/en
dc.rightsCopyright © International Foundation for Telemeteringen
dc.subjectPhase-locked loopsen
dc.subjectfrequency synthesizersen
dc.subjectfast frequency hoppingen
dc.titleA DIGITAL INTEGRATOR FOR AN S-BAND HIGH-SPEED FREQUENCY-HOPPING PHASE-LOCKED LOOPen_US
dc.typetexten
dc.typeProceedingsen
dc.contributor.departmentUniversity of Nevadaen
dc.contributor.departmentEmhiser Research, Incorporateden
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
refterms.dateFOA2018-09-11T08:59:01Z
html.description.abstractPhase-locked loop (PLL) frequency synthesizers used for high-speed data transmission must rapidly hop and lock to new frequencies. The fundamental problem is that the settling time depends inversely on the loop bandwidth, and increasing the bandwidth causes unwanted noise interference and stability problems for the circuit. We demonstrate the feasibility of replacing the analog integrator in the PLL with a digital integrator. This circuit has advantages of increased hopping speed, ability to compensate for temperature drift and system stability. PLL lock-in was demonstrated in a prototype circuit designed and built with both discrete components and with a programmable logic device.


Files in this item

Thumbnail
Name:
ITC_2003_03-14-01.pdf
Size:
173.7Kb
Format:
PDF

This item appears in the following Collection(s)

Show simple item record