Error Detection and error Correction Under the Conditions of Quarternary Decision Logic Techniques

Abstract

The hardware and theory of a multi-threshold bit decision technique called Quarternary Decision Logic are described. Quartenary Bit Decision Logic results in two simultaneous decisions on each received bit of a binary digital transmission: (1) a binary status decision; and, (2) a reliability decision which reflects on the presence/absence of multilation in the bit. Both decisions are based on a Shannon Integration of the received information over the whole bit interval. The ability to assess bit mutilation is then used to develop adjustable security-enforcing restraints on error correction and the receiving process itself. These restraints are developed by a Word Security Logic which keeps a "mutilation count" on each received word, The "mutilation count" per word results in a "Correction Permit/Inhibit" and a "Receiving Permit/Inhibit" output on each word. The "Correction Permit/ Inhibit" output bars error correction when the risk of a spurious correction is high. The "Receiving Permit/Inhibit” output blocks receiving when the risk of a direct evasion of security is high. The improvement in bit decision security and the improvements in security against spurious correction and direct evasions of Error detection are evaluated quantitatively in comparison to conventional single-threshold techniques, These improvements enable secure operation with lower redundancy coding systems because of the information gain which Quarternary Decision Logic provides. The possible contributions of Quarternary Decision Logic to self-adaptive data transmission systems and to automatic line equalization are explored in the section entitled "Conclusions".