TELEMETRY ACQUISITION BOARD INCLUDING REED-SOLOMON FPGA DECODER FOR SPACE APPLICATIONS
| dc.contributor.author | Lassère, François | * |
| dc.contributor.author | Ferréol, Max | * |
| dc.contributor.author | Rocher, Jean-Pierre | * |
| dc.date.accessioned | 2016-04-28T17:51:38Z | en |
| dc.date.available | 2016-04-28T17:51:38Z | en |
| dc.date.issued | 1999-10 | en |
| dc.identifier.issn | 0884-5123 | en |
| dc.identifier.issn | 0074-9079 | en |
| dc.identifier.uri | http://hdl.handle.net/10150/607329 | en |
| dc.description | International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada | en_US |
| dc.description.abstract | In order to reduce the ground segment equipment cost for small space missions, the French national space center (CNES) had the need to develop a CCSDS down-link interface board for low telemetry rates (< 1.5 Mb/s). This board performs frame synchronization and Reed-Solomon decoding. An important part of this design was the Reed-Solomon decoder development. In order to maintain low recurrent cost for this board, this decoder was realized in FPGA technology. Reed-Solomon decoding function, interleaving function (from 1 to 5) and virtual fill management are included in the same component. All set-up parameters are software programmable via the PCI bus, data and status are also available via the PCI bus under windows NT operating system. This paper presents the main features of this board and an overview of the Reed-Solomon decoder development. | |
| dc.description.sponsorship | International Foundation for Telemetering | en |
| dc.language.iso | en_US | en |
| dc.publisher | International Foundation for Telemetering | en |
| dc.relation.url | http://www.telemetry.org/ | en |
| dc.rights | Copyright © International Foundation for Telemetering | en |
| dc.subject | CCSDS | en |
| dc.subject | Reed-Solomon | en |
| dc.subject | FPGA | en |
| dc.subject | PCI bus | en |
| dc.title | TELEMETRY ACQUISITION BOARD INCLUDING REED-SOLOMON FPGA DECODER FOR SPACE APPLICATIONS | en_US |
| dc.type | text | en |
| dc.type | Proceedings | en |
| dc.contributor.department | Centre National d’Etudes Spatiales | en |
| dc.identifier.journal | International Telemetering Conference Proceedings | en |
| dc.description.collectioninformation | Proceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection. | en |
| refterms.dateFOA | 2018-06-20T07:20:28Z | |
| html.description.abstract | In order to reduce the ground segment equipment cost for small space missions, the French national space center (CNES) had the need to develop a CCSDS down-link interface board for low telemetry rates (< 1.5 Mb/s). This board performs frame synchronization and Reed-Solomon decoding. An important part of this design was the Reed-Solomon decoder development. In order to maintain low recurrent cost for this board, this decoder was realized in FPGA technology. Reed-Solomon decoding function, interleaving function (from 1 to 5) and virtual fill management are included in the same component. All set-up parameters are software programmable via the PCI bus, data and status are also available via the PCI bus under windows NT operating system. This paper presents the main features of this board and an overview of the Reed-Solomon decoder development. |
