An IF Sampling Digital Receiver Implementation for Space-based Command and Telemetry Applications

Abstract

This paper describes an approach to the implementation of an IF sampling digital receiver for low data rate command and telemetry applications in the NASA Goddard Spaceflight Tracking and Data Network (STDN) and Air Force Space-Ground Link System (SGLS). The digital design is targeted for an FPGA-based implementation and was written entirely in VHDL. Several size and clock reduction techniques are described which were utilized due to limited gate-array resources and power. The system-level design architecture is described followed by a discussion of algorithms and performance of critical stages in the receiver chain. Bit error performance of the prototype receiver is also presented. Finally, although this design is specifically targeted for a narrowband command and telemetry application, the methodology forms the basis of a configurable receiver for higher data rate applications.