AffiliationCalifornia Institute of Technology
National Aeronautics Space Adminstration
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Collection InformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.
AbstractDue to rapidly increasing downlink data rates between spacecraft and ground stations, the National Aeronautics and Space Administration (NASA) has developed an all-digital variable data rate receiver. The majority of the receiver is implemented on a single complementary metal oxide semiconductor (CMOS) application specific integrated circuit (ASIC) that is capable of processing data rates in excess of 300 mega-symbols per second or 600 mega-bits per second (Mbps) using quadrature phase-shift keyed (QPSK) modulation [1-5]. Developed jointly by the Goddard Space Flight Center and the Jet Propulsion Laboratory, the high rate digital demodulator (HRDD) ASIC uses parallel processing algorithms, which combined we call the advanced parallel receiver architecture (APRX), to perform the necessary functions of a satellite communications receiver. An overview of the next generation of the advanced parallel receiver architecture (APRX) is presented here, including a new parallel adaptive equalizer currently being implemented. The next generation receiver implementing this architecture will process in excess of 600 Megasymbols per second; the ASIC will process in excess of 1.2 Gbps using quadrature amplitude modulation (QPSK) and 2.4 Gbps using 16-quadrature amplitude modulation (QAM). The majority of the functions of the receiver are performed in the next generation high rate digital demodulator ASIC. A key property of such high data rate wireless communications systems is the use bandwidth efficient modulations often achieved through the use of sophisticated pulseshaping. The next generation ASIC, like the current generation ASIC, is designed to have programmable matched filters. The detection/matched filter bank in the ASIC should be programmed to “match” the received pulse-shape. This is particularly important for good biterror- rate performance in systems employing higher order modulations, such as 16-QAM employing partial-response pulse-shaping spanning many symbols. Such bandwidth efficient pulse-shaping methods require many coefficients in the matched filter; this creates increased computation and complexity in the receiver. Often such ideal receivers are not practical or possible to implement, and sub-optimal detection filtering techniques must be used. We will demonstrate that the use of a sub-optimum or truncated matched filter in some systems introduces severe intersymbol interference (ISI) distortion that results in poor BER results. However, we demonstrate for a specific pulse-shaped 16-QAM that if the demodulated baseband symbols are processed with a relatively simple equalizer very good performance may be achieved. The overall system complexity of such a system may be much lower than implementing the true matched filter . Finally we present an overview of the next generation advanced parallel receiver (APRX) capable of demodulating such pulse-shaped 16-QAM that includes a novel parallel adaptive equalizer.
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