A Multiple FSK Microprocessor Demodulator/Decoder

Abstract

A demodulator is described that utilizes an interrupt-driven 8-bit microprocessor and an external digital counter to demodulate an 8-ary Frequency-Shift-Keyed input signal. After demodulation, the system correlates received groups of symbols with a stored code to derive and maintain character synchronization, and compute the decoded and error corrected output. The total device package count is less than 10, including the microprocessor with integral read/write memory and clock driver circuits, a Parallel Interface Adapter, a 1024 X 8-bit ROM, an 8-bit digital counter, a two-pole filter, a limiter and complete input and output buffering.