Wafer Integrated Semiconductor Mass Memory

Abstract

This paper describes a light-weight, small-volume, low-power semiconductor mass memory which will provide high reliability operation in a variety of environments. The memory employs two new technologies: adaptive wafer scale integration where large numbers of memory arrays are interconnected on the wafer substrate using nonvolatile latching circuits; and a nonvolatile charge-coupled device memory element. The nonvolatile charge-coupled devices and peripheral circuitry are fabricated on a single silicon substrate using metal-nitride-oxide-semiconductor (MNOS) transistor structures. The adaptive latching circuits enable malfunctioning arrays to be replaced in situ by spare arrays which are available on the wafer substrate through the use of error detection/ correction circuitry. The paper also describes a specification for a spaceborne mass memory system including peripheral circuits. A memory system with a gigabit data storage capacity (total active storage elements = 1.2 gigabits can be fabricated within 0.6 cubic feet at an estimated weight of 26 pounds.