AffiliationIndian Space Research Organisation
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AbstractThis paper describes the design of a PC plug-in card that incorporates all functions of the base band segment of a PCM decommutator which includes the bit synchroniser (BS), frame synchroniser (FS) and subframe synchroniser (SFS). FPGAs are used for the realization of the digital sections of the circuit. The card is capable of handling all standard IRIG codes. The bit synchroniser can handle data rates upto 1Mbps (NRZL), while the frame and subframe synchronisers have been designed to work upto 10 Mbps.
SponsorsInternational Foundation for Telemetering