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    Shrinking the Cost of Telemetry Frame Synchronization

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    Author
    Ghuman, Parminder
    Bennett, Toby
    Solomon, Jeff
    Affiliation
    NASA, Goddard Space Flight Center
    RMS Technologies Inc.
    Issue Date
    1995-11
    Keywords
    Frame Synchronization
    Telemetry Processing
    VLSI
    ASIC
    Low Cost
    
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    Rights
    Copyright © International Foundation for Telemetering
    Collection Information
    Proceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.
    Publisher
    International Foundation for Telemetering
    Journal
    International Telemetering Conference Proceedings
    Abstract
    To support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) targeted to dramatically lower the cost of telemetry frame synchronization. This single VLSI device, known as the Parallel Integrated Frame Synchronizer (PIFS) chip, integrates most of the functionality contained in high density 9U VME card frame synchronizer subsystems currently in use. In 1987, a first generation 20 Mbps VMEBus frame synchronizer based on 2.0 micron CMOS VLSI technology was developed by Data Systems Technology Division. In 1990, this subsystem architecture was recast using 0.8 micron ECL & GaAs VLSI to achieve 300 Mbps performance. The PIFS chip, based on 0.7 micron CMOS technology, will provide a superset of the current VMEBus subsystem functions at rates up to 500 Mbps at approximately one-tenth current replication costs. Functions performed by this third generation device include true and inverted 64 bit marker correlation with programmable error tolerances, programmable frame length and marker patterns, programmable search-check-lock-flywheel acquisition strategy, slip detection, and CRC error detection. Acquired frames can optionally be annotated with quality trailer and time stamp. A comprehensive set of cumulative accounting registers are provided on-chip for data quality monitoring. Prototypes of the PIFS chip are expected in October 1995. This paper will describe the architecture and implementation of this new low-cost high functionality device.
    Sponsors
    International Foundation for Telemetering
    ISSN
    0884-5123
    0074-9079
    Additional Links
    http://www.telemetry.org/
    Collections
    International Telemetering Conference Proceedings, Volume 31 (1995)

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