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dc.contributor.authorHaas, W. H.
dc.contributor.authorLiao, H. H.
dc.contributor.authorSchoknecht, W. E.
dc.date.accessioned2016-06-09T18:08:35Z
dc.date.available2016-06-09T18:08:35Z
dc.date.issued1983-10
dc.identifier.issn0884-5123
dc.identifier.issn0074-9079
dc.identifier.urihttp://hdl.handle.net/10150/612436
dc.descriptionInternational Telemetering Conference Proceedings / October 24-27, 1983 / Sheraton-Harbor Island Hotel and Convention Center, San Diego, Californiaen_US
dc.description.abstractNumerous future space-based systems are being conceived that will require the on-board processing of a volume of data many orders of magnitude greater than the current state-ofthe- art. Such systems must in addition be extremely low power and autonomously fault recoverable. This paper describes a microprocessor-based distributed architecture that has been evolving as a solution to this problem. This proposed architecture features three subarchitectures: synchronous pipeline, dedicated-channel microprocessor array, and multiplebus oriented microcomputer array; as well as internal data compression, distributed control and self testing, and a building block approach to system implementation. Emphasized is the roll of microprocessors in this architecture and the challenge of reducing the overhead required by fault-tolerant processing.
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.language.isoen_USen
dc.publisherInternational Foundation for Telemeteringen
dc.relation.urlhttp://www.telemetry.org/en
dc.rightsCopyright © International Foundation for Telemeteringen
dc.titleLOW-POWER FAULT-TOLERANT MICROPROCESSOR-BASED DISTRIBUTED ARCHITECTURE FOR ON-BOARD SIGNAL PROCESSINGen_US
dc.typetexten
dc.typeProceedingsen
dc.contributor.departmentRockwell Internationalen
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
refterms.dateFOA2018-06-12T22:45:14Z
html.description.abstractNumerous future space-based systems are being conceived that will require the on-board processing of a volume of data many orders of magnitude greater than the current state-ofthe- art. Such systems must in addition be extremely low power and autonomously fault recoverable. This paper describes a microprocessor-based distributed architecture that has been evolving as a solution to this problem. This proposed architecture features three subarchitectures: synchronous pipeline, dedicated-channel microprocessor array, and multiplebus oriented microcomputer array; as well as internal data compression, distributed control and self testing, and a building block approach to system implementation. Emphasized is the roll of microprocessors in this architecture and the challenge of reducing the overhead required by fault-tolerant processing.


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