AN ORGANIZED APPROACH TO HARDWARE DIAGNOSTIC DESIGN

Abstract

The built-in diagnostic test has taken on an increased role as a maintenance tool in today’s complex electronic systems. While the ultimate diagnostic would exercise all of the major functions in a system and instantly isolate and identify any fault down to the specific part, many practical problems stand in the way. Using the diagnostic facility installed in a recent frame synchronizer/decommutator for the Jet Propulsion Laboratory (JPL) in Pasadena, the author attempts to show the logical approach, considerations, and compromises necessary to design the best possible diagnostic routine in a telemetry processor.