Open-Loop Nanosecond-Synchronization for Wideband Satellite Communications

Abstract

Successful satellite communication systems, providing service to thousands of users, must feature very inexpensive earth terminals. As many functions as possible must be transferred to the satellite, or a central control station, to reduce terminal complexity and cost. When satellite processors are used to demodulate, route, and error-correction decode and encode the communication channel data synchronization requirements can strongly affect system costs. Time Division Multiple Access (TDMA) is an efficient technique for efficiently distributing satellite services among many system users. Traditional TDMA synchronization techniques feature independent synchronization of each system communication data burst. This is expensive in terms of hardware complexity and system overhead efficiency. Demodulators and data bit-synchronizers must be designed to acquire during short burst preamble times, and unique-word-defectors must be provided to identify the burst time-division-multiplex reference. Burst preambles consume a significant portion of the available communication time, or force long frame periods with expensive buffers, as the number of independent communication channels becomes large. This paper discusses a synchronization technique for use with an onboard processing satellite communication system. The satellite oscillator is used as the system time reference, and as the frequency source for all downlink carriers and data clocks. Downlink timing is established at each system earth terminal by a combination of carrier and dataclock tracking, and a downlink timing epoch signal consisting of one bit per TDMA data burst. Uplink timing is established by an open-loop range prediction process, utilizing precision ephemerides calculated and distributed by the central control station. Overall timing accuracy of the uplink signal at the satellite receiver of ±7 nanoseconds allows unambiguous identification of each data bit position in a 128 Mbps TDMA burst. This is accomplished with simple, inexpensive terminal hardware using available crystal oscillators for time/frequency references and digital synthesis techniques that may be implemented in digital LSI chips. This paper presents terminal hardware block diagrams, satellite block diagrams, and central control station algorithms for the required timing synchronization functions. Error budgets for the identified error sources are also presented.