Single Chip Fixed Frequency Bit Synchronizer

Abstract

Over the past several years programmable logic devices have become a very attractive alternative to the application specific, Very Large Scale Integrated (VLSI) design approach. This trend is mainly due to the low cost and short design to production cycle time. This paper will describe a single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device. The bit synchronizer presented here is modeled after a Digital Transition Tracking Loop (DTTL) for symbol estimation, and employs a first-order Incremental Phase Modulator (IPM) for closed-loop symbol synchronization. Although the material presented below focuses on square wave subcarriers, with the appropriate modifications, this synchronizer will also process NRZ symbols. The Bit Error Rate (BER) and tracking performance is modeled and compared to optimum designs. The bit synchronizer presented here was developed for the Space Transportation System program under contract NAS5-27600 for meteorological data evaluation from the European Space Agency's (ESA) METEOSAT Spacecraft.