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dc.contributor.authorButler, Madeline J.
dc.contributor.authorJames, Calvin L.
dc.date.accessioned2016-06-24T21:19:38Z
dc.date.available2016-06-24T21:19:38Z
dc.date.issued1989-11
dc.identifier.issn0884-5123
dc.identifier.issn0074-9079
dc.identifier.urihttp://hdl.handle.net/10150/614687
dc.descriptionInternational Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, Californiaen_US
dc.description.abstractOver the past several years programmable logic devices have become a very attractive alternative to the application specific, Very Large Scale Integrated (VLSI) design approach. This trend is mainly due to the low cost and short design to production cycle time. This paper will describe a single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device. The bit synchronizer presented here is modeled after a Digital Transition Tracking Loop (DTTL) for symbol estimation, and employs a first-order Incremental Phase Modulator (IPM) for closed-loop symbol synchronization. Although the material presented below focuses on square wave subcarriers, with the appropriate modifications, this synchronizer will also process NRZ symbols. The Bit Error Rate (BER) and tracking performance is modeled and compared to optimum designs. The bit synchronizer presented here was developed for the Space Transportation System program under contract NAS5-27600 for meteorological data evaluation from the European Space Agency's (ESA) METEOSAT Spacecraft.
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.language.isoen_USen
dc.publisherInternational Foundation for Telemeteringen
dc.relation.urlhttp://www.telemetry.org/en
dc.rightsCopyright © International Foundation for Telemeteringen
dc.titleSingle Chip Fixed Frequency Bit Synchronizeren_US
dc.typetexten
dc.typeProceedingsen
dc.contributor.departmentGoddard Space Flight Centeren
dc.contributor.departmentBendix Field Engineering Corp.en
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
refterms.dateFOA2018-06-13T00:00:18Z
html.description.abstractOver the past several years programmable logic devices have become a very attractive alternative to the application specific, Very Large Scale Integrated (VLSI) design approach. This trend is mainly due to the low cost and short design to production cycle time. This paper will describe a single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device. The bit synchronizer presented here is modeled after a Digital Transition Tracking Loop (DTTL) for symbol estimation, and employs a first-order Incremental Phase Modulator (IPM) for closed-loop symbol synchronization. Although the material presented below focuses on square wave subcarriers, with the appropriate modifications, this synchronizer will also process NRZ symbols. The Bit Error Rate (BER) and tracking performance is modeled and compared to optimum designs. The bit synchronizer presented here was developed for the Space Transportation System program under contract NAS5-27600 for meteorological data evaluation from the European Space Agency's (ESA) METEOSAT Spacecraft.


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