High Speed VLSI Systems for NASA's Telemetry Return Link Processor

Abstract

In the upcoming Space Station Freedom (SSF) era, NASA will require many new data systems capable of performing basic data handling functions such as Frame Synchronization, Frame Error Detection & Correction, and Multiplexing/Demultiplexing at rates in the hundreds of Megabits per second (Mbps) range. The Data Interface Facility (DIF) is a key element in NASA's advanced communications systems. The DIF will support communications between the space elements and multiple ground facilities. This paper will describe the architecture of the DIF and its core element, the Return Link Processor (RLP). Current activities to prototype some of the primary functions of the RLP will be presented. Finally, the paper will show how the prototype elements could be integrated into a full performance DIF RLP.