THE APPLICATION OF RISC ARCHITECTURES TO REAL-TIME TELEMETRY PROCESSING

Abstract

The number and types of processes carried out on telemetered data in real time have increased in direct proportion to the available processing speeds. Operations following decommutation in the data pipeline are often referred to generically as Engineering Units Processing (EUP). Examples of the types of functions typically performed by an EUP are data compression, polynomial conversion, and with the advent of message data, desyllabification. Real-time telemetry processing, such as EUP, has traditionally been done on bitslice processors, primarily because they possessed the speed required to maintain pace with the relatively high data rates. As data rates continue to increase, the need for bitslice processors with even higher processing speeds would seem to be even more pressing. However, in recent years RISC (Reduced Instruction Set Computer) based microprocessors have been developed that approach bit-slice processing rates and possess certain advantages. The advantages of a RISC based approach to real-time telemetry processing include ease of programming, shorter design and implementation cycles, and a direct path to speed increases as silicon processing technology advances. In addition, the streaming nature of the data to be operated on, and the EUP requirements generate a multi-branched program structure creating the potential for a high degree of optimization within a pipelined processor architecture. While most RISC applications are currently programmed in assembly language to take full advantage of the hardware, it is expected that improvements in optimizing compilers in the future will further enhance the position of RISC with respect to bit-slice processing.