Show simple item record

dc.contributor.authorMalatesta, William A.
dc.date.accessioned2016-06-27T20:10:30Z
dc.date.available2016-06-27T20:10:30Z
dc.date.issued1989-11
dc.identifier.issn0884-5123
dc.identifier.issn0074-9079
dc.identifier.urihttp://hdl.handle.net/10150/614850
dc.descriptionInternational Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, Californiaen_US
dc.description.abstractThe number and types of processes carried out on telemetered data in real time have increased in direct proportion to the available processing speeds. Operations following decommutation in the data pipeline are often referred to generically as Engineering Units Processing (EUP). Examples of the types of functions typically performed by an EUP are data compression, polynomial conversion, and with the advent of message data, desyllabification. Real-time telemetry processing, such as EUP, has traditionally been done on bitslice processors, primarily because they possessed the speed required to maintain pace with the relatively high data rates. As data rates continue to increase, the need for bitslice processors with even higher processing speeds would seem to be even more pressing. However, in recent years RISC (Reduced Instruction Set Computer) based microprocessors have been developed that approach bit-slice processing rates and possess certain advantages. The advantages of a RISC based approach to real-time telemetry processing include ease of programming, shorter design and implementation cycles, and a direct path to speed increases as silicon processing technology advances. In addition, the streaming nature of the data to be operated on, and the EUP requirements generate a multi-branched program structure creating the potential for a high degree of optimization within a pipelined processor architecture. While most RISC applications are currently programmed in assembly language to take full advantage of the hardware, it is expected that improvements in optimizing compilers in the future will further enhance the position of RISC with respect to bit-slice processing.
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.language.isoen_USen
dc.publisherInternational Foundation for Telemeteringen
dc.relation.urlhttp://www.telemetry.org/en
dc.rightsCopyright © International Foundation for Telemeteringen
dc.titleTHE APPLICATION OF RISC ARCHITECTURES TO REAL-TIME TELEMETRY PROCESSINGen_US
dc.typetexten
dc.typeProceedingsen
dc.contributor.departmentVeda Incorporateden
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
refterms.dateFOA2018-07-02T03:29:19Z
html.description.abstractThe number and types of processes carried out on telemetered data in real time have increased in direct proportion to the available processing speeds. Operations following decommutation in the data pipeline are often referred to generically as Engineering Units Processing (EUP). Examples of the types of functions typically performed by an EUP are data compression, polynomial conversion, and with the advent of message data, desyllabification. Real-time telemetry processing, such as EUP, has traditionally been done on bitslice processors, primarily because they possessed the speed required to maintain pace with the relatively high data rates. As data rates continue to increase, the need for bitslice processors with even higher processing speeds would seem to be even more pressing. However, in recent years RISC (Reduced Instruction Set Computer) based microprocessors have been developed that approach bit-slice processing rates and possess certain advantages. The advantages of a RISC based approach to real-time telemetry processing include ease of programming, shorter design and implementation cycles, and a direct path to speed increases as silicon processing technology advances. In addition, the streaming nature of the data to be operated on, and the EUP requirements generate a multi-branched program structure creating the potential for a high degree of optimization within a pipelined processor architecture. While most RISC applications are currently programmed in assembly language to take full advantage of the hardware, it is expected that improvements in optimizing compilers in the future will further enhance the position of RISC with respect to bit-slice processing.


Files in this item

Thumbnail
Name:
ITC_1989_89-0849.pdf
Size:
31.15Kb
Format:
PDF

This item appears in the following Collection(s)

Show simple item record