Show simple item record

dc.contributor.authorHorn, Paul*
dc.date.accessioned2016-06-29T17:28:51Z
dc.date.available2016-06-29T17:28:51Z
dc.date.issued1988-10
dc.identifier.issn0884-5123
dc.identifier.issn0074-9079
dc.identifier.urihttp://hdl.handle.net/10150/615031
dc.descriptionInternational Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevadaen_US
dc.description.abstractRecent developments in electronics have made possible the miniaturization of many of the subsystem components associated with a typical spacecraft data acquisition and control system. This paper describes a low power consumption, fault tolerant, high performance data acquisition and control system design utilizing third generation hardware. The system includes built in test autonomy, redundancy management and fault tolerant communication busses, and supports multiprocessing with up to five 35 Million instructions per second (Mips) processors.
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.language.isoen_USen
dc.publisherInternational Foundation for Telemeteringen
dc.relation.urlhttp://www.telemetry.org/en
dc.rightsCopyright © International Foundation for Telemeteringen
dc.titleApplication for Spacecraft of the 90's Using MicroDACS Technologyen_US
dc.typetexten
dc.typeProceedingsen
dc.contributor.departmentSCI Technology Inc.en
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
refterms.dateFOA2018-05-28T08:22:45Z
html.description.abstractRecent developments in electronics have made possible the miniaturization of many of the subsystem components associated with a typical spacecraft data acquisition and control system. This paper describes a low power consumption, fault tolerant, high performance data acquisition and control system design utilizing third generation hardware. The system includes built in test autonomy, redundancy management and fault tolerant communication busses, and supports multiprocessing with up to five 35 Million instructions per second (Mips) processors.


Files in this item

Thumbnail
Name:
ITC_1988_88-014.pdf
Size:
52.70Kb
Format:
PDF

This item appears in the following Collection(s)

Show simple item record