VLSI High Speed Packet Processor

Abstract

The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a Packet Processor card utilizing semi-custom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multi-channel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the Packet Processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semi-custom VLSI logic.