Evolutionary Factors in the Development of a Realtime Multiprocessor System

Abstract

Architectural decisions made three years ago in the design of a high speed preprocessor system for realtime data processing at sustained rates of 200k to 300k parameters per second were driven by the need to provide expansion flexibility and to permit the user to program application algorithms through the use of a high level language. The original design concept was a two bus architecture which would accept and merge data from up to 8 data sources with the required number of parallel computers driven by the realtime processing needs - not the 1.5M wps aggregate throughput capability. Other configuration variables were to enable the use of an optional raw data circular (wrap around) file for intermaneuver or anomaly analysis, the number of analog and discrete outputs for strip chart and visual displays, and the ability to support a wide range of processed data throughputs to one or more host computers. As a result of future defined requirements, the expansion capability ultimately grew to allow up to 30 data sources, 256 analog outputs, and 196 discrete outputs. A concurrent study of the engine and airborne test community showed that in many applications over 50% of the processing was restricted to repetitive computations such as FFTs and first order EU conversions. Although bit slice processors were much faster than general purpose Application Processors (APs), nobody in the user community said they wanted to write microcode to install their application programs. As the first customer's requirements could be easily handled by adding a few APs, the initial system design concentrated only on general purpose processors with provisions being made for the future addition of special purpose digital signal processors to co-reside with the general purpose APs. At the some time, much of the rotary wing test community's data processing was highly floating point intensive so the AP processor was designed with an independent floating point processor using the fastest possible device technology. The original two bus architecture using industry standard Versa and VME buses evolved as the design matured to a six bus architecture capable of supporting up to 60 parallel processors. The use of industry standard buses has permitted successful development of configurations using a wide range of third party processors and peripherals from a variety of sources. Larger system configurations are implemented by a multi-chassis structure with functions arranged so that no realtime bus is unterminated or physically longer than 19 inches. The simultaneous software development supporting these changes and encompassing 25 man-years of work is beyond the scope of this paper and will be covered in a separate publication.