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dc.contributor.authorHsu, Cherng-Shung
dc.contributor.authorLiang, Junn-Kuen
dc.contributor.authorLu, Fu-Chao
dc.date.accessioned2016-07-05T19:34:24Z
dc.date.available2016-07-05T19:34:24Z
dc.date.issued1986-10
dc.identifier.issn0884-5123
dc.identifier.issn0074-9079
dc.identifier.urihttp://hdl.handle.net/10150/615558
dc.descriptionInternational Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevadaen_US
dc.description.abstractIn this paper, the 70 MHz IF differential binary phase shift keying (DBPSK) modem is designed and implemented. At the transmitter, the data are first differentially encoded, and then sent to the binary phase modulator, which is followed by a delicatedly designed band pass filter to suppress the undesired sideband spectrum. At the receiver, the DBPSK signal is coherently demodulated by a Costas loop which is carefully analyzed and designed in this paper. In order to maintain the overall loop gain within a desired range for keeping a better loop performance, an IF preconditioning AGC (Automatic Gain Control) circuit is added in the demodulator to keep the IF amplifier output level almost constant even at low signal to noise ratio. In order to improve the false lock due to the data sideband, especially for low rate modems, and to enhance acquisition, a modified Costas loop and an automatic sweep search acquisition circuit are included in the demodulator. Besides the carrier recovery, the bit rate clock must be recovered from the received DBPSK signal. Instead of serial processing, i.e., clock recovery comes after carrier recovery, a parallel processing of the received DBPSK signal is employed, i.e., clock recovery is parallel to carrier recovery. In other words, the carrier and clock recovery circuits independently process the same received DBPSK signal at the same time. The advantages obtained from the parallel processing are faster overall system acquisition and reduction of information loss. The recovered clock is derived from a bandlimited DBPSK signal by an envelope detector followed by a phase-locked loop (PLL). The key features of this suboptimum clock recovery circuits are simplicity and low cost for practical hardware implementation. An example for modem design will be given and the modem will be implemented and then tested. Parameters selection and hardware implementation of important building blocks in the modem circuit are all given careful consideration. Furthermore, the block of the IF AGC, modified Costas loop scheme and sweep search circuits will also be described with emphasis on their key functions. Finally, the bit error rate performance of the experimently implemented modem will be tested and presented.
dc.description.sponsorshipInternational Foundation for Telemeteringen
dc.language.isoen_USen
dc.publisherInternational Foundation for Telemeteringen
dc.relation.urlhttp://www.telemetry.org/en
dc.rightsCopyright © International Foundation for Telemeteringen
dc.titleIF DBPSK Modems Design for Command Link and Telemetry Systemsen_US
dc.typetexten
dc.typeProceedingsen
dc.contributor.departmentChung Shan Institute of Science and Technologyen
dc.identifier.journalInternational Telemetering Conference Proceedingsen
dc.description.collectioninformationProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection.en
refterms.dateFOA2018-04-26T13:39:21Z
html.description.abstractIn this paper, the 70 MHz IF differential binary phase shift keying (DBPSK) modem is designed and implemented. At the transmitter, the data are first differentially encoded, and then sent to the binary phase modulator, which is followed by a delicatedly designed band pass filter to suppress the undesired sideband spectrum. At the receiver, the DBPSK signal is coherently demodulated by a Costas loop which is carefully analyzed and designed in this paper. In order to maintain the overall loop gain within a desired range for keeping a better loop performance, an IF preconditioning AGC (Automatic Gain Control) circuit is added in the demodulator to keep the IF amplifier output level almost constant even at low signal to noise ratio. In order to improve the false lock due to the data sideband, especially for low rate modems, and to enhance acquisition, a modified Costas loop and an automatic sweep search acquisition circuit are included in the demodulator. Besides the carrier recovery, the bit rate clock must be recovered from the received DBPSK signal. Instead of serial processing, i.e., clock recovery comes after carrier recovery, a parallel processing of the received DBPSK signal is employed, i.e., clock recovery is parallel to carrier recovery. In other words, the carrier and clock recovery circuits independently process the same received DBPSK signal at the same time. The advantages obtained from the parallel processing are faster overall system acquisition and reduction of information loss. The recovered clock is derived from a bandlimited DBPSK signal by an envelope detector followed by a phase-locked loop (PLL). The key features of this suboptimum clock recovery circuits are simplicity and low cost for practical hardware implementation. An example for modem design will be given and the modem will be implemented and then tested. Parameters selection and hardware implementation of important building blocks in the modem circuit are all given careful consideration. Furthermore, the block of the IF AGC, modified Costas loop scheme and sweep search circuits will also be described with emphasis on their key functions. Finally, the bit error rate performance of the experimently implemented modem will be tested and presented.


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