PCM SIMULATOR ARCHITECTURE REDUCES SETUP COMPLEXITY

Abstract

The advent of Bit Slice Processors and related architectures has produced numerous high performance PCM Data Simulators. Many of these fall into the category of stored program simulators, which give the user unlimited flexibility and power. These simulators allow the user to program almost any imaginable format, with combinations of subframes, subsubframes, and asynchronously embedded subframes. The drawback is that the user is forced to program the simulator using a very detailed machine level language which usually has no obvious relation to PCM frame formats. A new simulator architecture allows the user to describe the frame format to be simulated in familiar terms. This eliminates the need to learn yet another programming language or develop a Compiler. The user identifies common parameters such as frame length, subframe length, and where special words should be located. These special words can be unique sensor data words, a table of sensor data, ID counters, subframe slots and so on.