QUATERNARY SHIFT REGISTER AND ITS APPLICATION TO DIGITAL SIGNAL PROCESSING
AffiliationBoston University College of Engineering
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AbstractThis paper will describe the design of a quaternary memory cell and a quaternary shift register. The concept used here is based on multiple-valued logic algebra, which can be extended to a design of other high radix memory cells and high radix shift registers. A comparison of the quaternary memory cell and quaternary shift register with its binary counterpart will be discussed. The reduction of device counts and interconnections in quaternary systems promisses a good future in digital signal processing and communication network design realized by VLSI technology.
SponsorsInternational Foundation for Telemetering