Set-Associative History-Aided Adaptive Replacement for On-Chip Caches
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PublisherThe University of Arizona.
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AbstractLast Level Caches (LLCs) are critical to reducing processor stalls to off-chip memory and improving processing throughput, and replacement policy plays an important role in the performance of LLCs. Many replacement algorithms are designed to be thrash-resistant to protect the working set in the cache from scans, but a fundamental challenge is balancing thrash-resistance to changes to the working set over time as an application executes. In this thesis a novel Set-Associative History-Aided Adaptive Replacement Cache (SHARC) LLC replacement algorithm is proposed, which adjusts scan-resistance at run-time based on the current memory access properties of the application. This policy segregates the cache to protect the working set from scans and utilizes history information from recently evicted cache lines to increase or decrease amount of cache reserved for the working set. On average, SHARC improves IPC by approximately 11% over LRU replacement policy while only requiring 14% increase in overhead. The SHARC-NRU replacement policy is also proposed to reduce this overhead and achieves approximately 10% performance improvement and requires 11% less overhead than LRU.
Degree ProgramGraduate College
Electrical & Computer Engineering