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    Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media

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    Name:
    TCOM_Error_errore_eicitur_R2_v ...
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    Final Accepted Manuscript
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    Author
    Ivanis, Predrag
    Vasic, Bane
    Affiliation
    Univ Arizona, Dept Elect & Comp Engn
    Issue Date
    2016-09
    Keywords
    Faulty hardware
    Gallager-B decoding
    LDPC codes
    Markov chains
    unreliable logic
    
    Metadata
    Show full item record
    Publisher
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
    Citation
    Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media 2016, 64 (9):3596 IEEE Transactions on Communications
    Journal
    IEEE Transactions on Communications
    Rights
    © 2016 IEEE.
    Collection Information
    This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.
    Abstract
    We give an architecture of a storage system consisting of a storage medium made of unreliable memory elements and an error correction circuit made of a combination of noisy and noiseless logic gates that is capable of retaining the stored information with the lower probability of error than a storage system with a correction circuit made completely of noiseless logic gates. Our correction circuit is based on the iterative decoding of low-density parity check codes, and uses the positive effect of errors in logic gates to correct errors in memory elements. In the spirit of Marcus Tullius Cicero's Clavus clavo eicitur (one nail drives out another), the proposed storage system operates on the principle: error errore eicitur-one error drives out another. The randomness that is present in the logic gates makes these classes of decoders superior to their noiseless counterparts. Moreover, random perturbations do not require any additional computational resources as they are inherent to unreliable hardware itself. To utilize the benefits of logic gate failures, our correction circuit relies on two key novelties: a mixture of reliable and unreliable gates and decoder rewinding. We present a method based on absorbing Markov chains for the probability of error analysis, and explain how the randomness in the variable and check node update function helps a decoder to escape to local minima associated with trapping sets.
    ISSN
    0090-6778
    DOI
    10.1109/TCOMM.2016.2590547
    Version
    Final accepted manuscript
    Sponsors
    European Union [309129]; IUSSTF under the Indo-US Joint R&D Network Joint Centre on Data Storage Research Award [16-2014]; NSF [CCF-0963726, CCF-1314147, ECCS-1500170]; Serbian Ministry of Science [TR32028]
    Additional Links
    http://ieeexplore.ieee.org/document/7509624/
    ae974a485f413a2113503eed53cd6c53
    10.1109/TCOMM.2016.2590547
    Scopus Count
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    UA Faculty Publications

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