FPGA implementation of advanced FEC schemes for intelligent aggregation networks
AffiliationUniv Arizona, Dept Elect & Comp Engn
low-density parity-check (LDPC) codes
intelligent aggregation networks
MetadataShow full item record
PublisherSPIE-INT SOC OPTICAL ENGINEERING
CitationDing Zou and Ivan B. Djordjevic " FPGA implementation of advanced FEC schemes for intelligent aggregation networks ", Proc. SPIE 9773, Optical Metro Networks and Short-Haul Systems VIII, 977309 (February 13, 2016); doi:10.1117/12.2214884; http://dx.doi.org/10.1117/12.2214884
Rights© 2016 SPIE.
Collection InformationThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at email@example.com.
AbstractIn state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10(-15) in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.
VersionFinal published version