I/O Aware Power Shifting
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Lavoie_Power_Shifting.pdf
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Final Accepted Manuscript
Affiliation
Dept. of Comput. Sci., Univ. of ArizonaIssue Date
2016-05Keywords
parallel processingpower aware computing
I/O aware power shifting
fixed power bound
high-performance computing
phase frequency
Algorithm design and analysis
Clustering algorithms
Data visualization
DelaysHeuristic algorithmsSchedulesHPCPerformancePower
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IEEECitation
L. Savoie et al., "I/O Aware Power Shifting," 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Chicago, IL, 2016, pp. 740-749.Rights
Copyright © 2016, IEEE.Collection Information
This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.Abstract
Power limits on future high-performance computing (HPC) systems will constrain applications. However, HPC applications do not consume constant power over their lifetimes. Thus, applications assigned a fixed power bound may be forced to slow down during high-power computation phases, but may not consume their full power allocation during low-power I/O phases. This paper explores algorithms that leverage application semantics-phase frequency, duration and power needs-to shift unused power from applications in I/O phases to applications in computation phases, thus improving system-wide performance. We design novel techniques that include explicit staggering of applications to improve power shifting. Compared to executing without power shifting, our algorithms can improve average performance by up to 8% or improve performance of a single, high-priority application by up to 32%.Note
No embargo.Version
Final accepted manuscriptAdditional Links
http://ieeexplore.ieee.org/document/7516070/Scopus Count
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