Forward Error Correction
Low-density parity-check codes
Orthogonal Frequency Division Multiplexing
AdvisorDjordjevic, Ivan B.
MetadataShow full item record
PublisherThe University of Arizona.
RightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
AbstractCurrent coherent optical transmission systems focus on single carrier solutions for 400Gb/s serial transmission to support traffic growth in fiber-optics communications, together with a few subcarriers multiplexed solutions for the 1 Tb/s serial data rates and beyond. With the advancement of analog-to-digital converter technologies, high order modulation formats up to 64-QAM with symbol rate up to 72Gbaud have been demonstrated experimentally with Raman amplification. To enable such high serial data rates, it is highly desirable to implement in hardware low complexity digital signal processing schemes and advanced forward error correction coding with powerful error correction capability. In this dissertation, to enable high-speed optical communications, we first proposed an efficient FPGA architecture of high-performance binary and non-binary LDPC engines that can support throughputs of multiple Gb/s, which have low power consumption, providing high net coding gains at a target bit-error rate of 10-15. Further, we implement a generalized LDPC coding based rate adaptive binary LDPC coding scheme and puncturing based rate adaptive non-binary LDPC coding scheme, where large number of parameters can be reconfigured in order to cope with the time-varying optical channel conditions and service requirements. Based on comprehensive analysis on complexity, latency, and power consumption we demonstrate that the proposed efficient implementation represents a feasible solution for the next generation optical communication networks. Additionally, we investigate the FPGA implementation of rate adaptive regular LDPC coding combined with up to six high-order modulation formats and demonstrate high net coding gain performance and demonstrated a bit loading algorithm for irregular LDPC coding. Lastly, we present the real-time implementation of a direct detection OFDM transceiver with multi Giga symbols/s symbol rates in a back-to-back configuration.
Degree ProgramGraduate College
Electrical & Computer Engineering