Browsing International Telemetering Conference Proceedings, Volume 53 (2017) by Authors
DEVELOPMENT OF A PORTABLE TM GROUND STATION FOR KSLV-II WITH A RS422-TO-ETHERNET TM PCM DECODER AND MAGALI TM SOFTWAREYoon, Wonju; Noh, Seongmin; Korea Aerospace Research Institute (International Foundation for Telemetering, 2017-10)The onboard telemetry (TM) system of Korea Space Launch Vehicle-II (KSLV-II) transmits PCM framedatatotheTMgroundstationviaRS422beforeﬂightorviaRFlinkduringﬂight. Thispaper describes the development of a portable TM ground station for KSLV-II that can decommutate the PCM frame data received via RS422. The developed portable TM ground station consists of two major components: a RS422-to-Ethernet TM PCM decoder and a laptop running MAGALI commercial TM software. The TM PCM decoder transforms a serial bit stream of the PCM data received via RS422 into multicast UDP packets. The MAGALI TM software supports an Ethernet acquisition module for the reception of the PCM frame data, which enables decommutation of the UDP packet-based PCM frame data received from the TM PCM decoder. Furthermore, the use of multicast UDP enables simultaneous decommutation of the PCM frame data at multiple laptops running MAGALI.
IMPLEMENTATION OF DIGITAL SIGNAL PROCESSING WITH HIGH DATA RATE SENSORS FOR DATA COMPRESSIONNoh, Seongmin; Yoo, Hoyoung; Korea Aerospace Research Institute; Chungnam National University (International Foundation for Telemetering, 2017-10)The onboard telemetry system of Korea Space Launch Vehicle-II (KSLV-II) acquires acoustic, vibration, and piezoelectric pressure sensors that require high data rate over several kilo samples per second, so the compression method is needed to expand link margin of telemetry system. This paper implements third-octave and FFT signal processing algorithms to reduce sensor data with high compression ratio depends on data acquisition requirements. The developed signal processing hardware module is composed of analog signal conditioning block and digital signal processing block on FPGA, and the digital block is fully implemented with dedicated hardware using HDL. For digital hardware implementation, multistage structure with ANSI standard octave filter bank is used for third-octave processing, and pipelined architecture is used for FFT. The performance of data acquisition and signal processing is evaluated and compared to the commercial data acquisition equipment.