Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications
AffiliationUniv Arizona, Dept Elect & Comp Engn
Univ Arizona, Dept Phys
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CitationJ. Wu, A. K. Kodi, S. Kaya, A. Louri, H. Xin, "Monopoles loaded with 3-D-Printed dielectrics for future wireless intrachip communications", IEEE Trans. Antennas Propag., vol. 65, no. 12, pp. 6838-6846, Dec. 2017.
RightsCopyright © 2017, IEEE
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AbstractWe propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated, and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.
VersionFinal accepted manuscript
SponsorsNational Science Foundation [ECCS-1408271, CCF-1513923, CCF-1054339, CCF-1420718, CCF-1318981, CCF1513606, CCF-1547034, CCF-1547035, CCF-1565273, CCF-1600820]