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dc.contributor.authorWu, Junqiang
dc.contributor.authorKodi, Avinash Karanth
dc.contributor.authorKaya, Savas
dc.contributor.authorLouri, Ahmed
dc.contributor.authorXin, Hao
dc.date.accessioned2018-06-25T16:55:35Z
dc.date.available2018-06-25T16:55:35Z
dc.date.issued2017-12
dc.identifier.citationJ. Wu, A. K. Kodi, S. Kaya, A. Louri, H. Xin, "Monopoles loaded with 3-D-Printed dielectrics for future wireless intrachip communications", IEEE Trans. Antennas Propag., vol. 65, no. 12, pp. 6838-6846, Dec. 2017.en_US
dc.identifier.issn0018-926X
dc.identifier.issn1558-2221
dc.identifier.doi10.1109/TAP.2017.2758400
dc.identifier.urihttp://hdl.handle.net/10150/628062
dc.description.abstractWe propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated, and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.en_US
dc.description.sponsorshipNational Science Foundation [ECCS-1408271, CCF-1513923, CCF-1054339, CCF-1420718, CCF-1318981, CCF1513606, CCF-1547034, CCF-1547035, CCF-1565273, CCF-1600820]en_US
dc.language.isoenen_US
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCen_US
dc.relation.urlhttp://ieeexplore.ieee.org/document/8055587/en_US
dc.rightsCopyright © 2017, IEEEen_US
dc.subject3-D printingen_US
dc.subjectantennasen_US
dc.subjectelectromagnetic propagationen_US
dc.subjectinterconnecten_US
dc.subjectintrachip communicationen_US
dc.subjectmultiprocessor interconnectionen_US
dc.subjectnetwork-on-chip (NoC)en_US
dc.titleMonopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communicationsen_US
dc.typeArticleen_US
dc.contributor.departmentUniv Arizona, Dept Elect & Comp Engnen_US
dc.contributor.departmentUniv Arizona, Dept Physen_US
dc.identifier.journalIEEE TRANSACTIONS ON ANTENNAS AND PROPAGATIONen_US
dc.description.collectioninformationThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.en_US
dc.eprint.versionFinal accepted manuscripten_US
dc.source.journaltitleIEEE Transactions on Antennas and Propagation
dc.source.volume65
dc.source.issue12
dc.source.beginpage6838
dc.source.endpage6846
refterms.dateFOA2018-06-25T16:55:36Z


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