Hard-Decision Decoding of LDPC Codes Under Timing Errors: Overview and New Results
AffiliationUniv Arizona, Dept Elect & Comp Engn
low-density parity-check codes
MetadataShow full item record
CitationS. Brkic, P. Ivanis and B. Vasić, "Hard-decision decoding of LDPC codes under timing errors: Overview and new results," 2017 25th Telecommunication Forum (TELFOR), Belgrade, 2017, pp. 1-8. doi: 10.1109/TELFOR.2017.8249332
RightsCopyright © 2017, IEEE
Collection InformationThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at email@example.com.
AbstractThis paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes built form unreliable logic gates. We assume that hardware unreliability comes from supply voltage reduction, which causes probabilistic gate failures, called timing errors. We are able to demonstrate robustness of simple Gallager B decoder to timing errors, when applied on codes free of small trapping sets, as well as positive effects that timing errors have on the decoding of codes with contain small trapping sets. Furthermore, we show that concept of guaranteed error correction can be applied to the decoders made partially from unreliable components. In contrast to the decoding under uncorrelated gate failures, we prove that bit-flipping decoding under timing errors can achieve arbitrary low error probability. Consequently, we formulate condition sufficient that memory architecture, which employs bit-flipping decoder, preserved all stored information.
VersionFinal accepted manuscript
SponsorsSerbian Ministry of Science [TR32028]; NSF [ECCS-1500170]; Indo-US Science and Technology Forum (IUSSTF) through the Joint Networked Center for Data Storage Research [JC-16-2014-US]