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PublisherThe University of Arizona.
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AbstractAdvances in semiconductor process technology in the past several decades have brought about an abundance of transistors that can be fabricated on a single silicon die. Microprocessor designers have been integrating more and more processing cores on-chip by taking advantage of such abundance. Network-on-Chip (NoC) has become a popular choice for connecting a large number of processing cores in chip multiprocessor designs. NoC provides many advantages over the traditional bus-based approach in terms of bandwidth, scalability, latency, etc. The central part of an NoC is the router. In a conventional NoC design, most of the router area is occupied by the buffers and the crossbar switch. Not surprisingly, these two components also consume the majority of the router’s power. Most of NoC research has been based on the conventional router microarchitecture in the areas of routing algorithm, resource allocation/arbitration, buffer design, etc. There has not been much work done on drastic router microarchitecture redesign. In this dissertation, a novel router microarchitecture design is proposed, which we call Omega, that treats the router itself as a small network of a ring topology. Omega is highly modular and much simpler than the conventional design. It does not use a large crossbar switch as in the conventional design; packet switching is done with simple muxes. Furthermore, the network packet latency is greatly reduced. Simulation and circuit synthesis show that the Omega microarchitecture can reduce latency, area and power by 53%, 34% and 27%, respectively, compared to the conventional design. The Omega microarchitecture design also provides opportunities to implement features that do not exist or are difficult to be realized in the conventional design. To demonstrate this, we implement a new feature on the Omega router to merge packets together in the buffer. The merged packets traverse the network together as long as their routes to destinations do not diverge. This greatly improves the buffer and link utilization. As a result, the effective network capacity can be substantially increased. This dissertation presents one of the first efforts on the new microarchitecture for router considering packet merging. Additional characterizations can be done to better understand its potentials for various applications, and perhaps its shortcomings, in future work to push performance even further.
Degree ProgramGraduate College
Electrical & Computer Engineering