COMPARISON OF FPGA EQUALIZER IMPLEMENTATIONS FOR HIGH-SPEED DATA TELEMETRY

Abstract

This paper examines the real-time implementation of equalization techniques. Telemetry RF channels are formidable due to the nature of desert test ranges – specifically due to multipath, changing path loss from environmental effects, and thermal distortions. This challenge is further complicated by the high velocity nature of test assets. Optimization of channel equalization in a real-time scenario is essential for high speed data telemetry over extended distances. This paper examines the mathematical background of equalization techniques and presents results based on FPGA implementations. The results were obtained from Vivado High Level Synthesis (HLS), which generates HDL from C/C++, as well as traditional VHDL coding. The contribution to the state of the art in this paper is the determination of the technological maturity of HLS versus traditional hand coding and the comparison of FPGA implementations of equalization algorithms against current platforms.