AffiliationUniv Arizona, Dept Elect & Comp Engn
majority logic decoding
probabilistic gate-output switching model
MetadataShow full item record
CitationS. Brkic, P. Ivaniš and B. Vasić, "Majority Logic Decoding Under Data-Dependent Logic Gate Failures," in IEEE Transactions on Information Theory, vol. 63, no. 10, pp. 6295-6306, Oct. 2017. doi: 10.1109/TIT.2017.2741466
Rights© 2017 IEEE.
Collection InformationThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at email@example.com.
AbstractA majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gateoutput switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.
VersionFinal accepted manuscript
SponsorsEuropean Union ; Serbian Ministry of Science [TR32028]; NSF [ECCS-1500170]; Indo-US Science and Technology Forum through the Joint Networked Center for Data Storage Research [JC-16-2014-US]