Engineering Design Program: Engine Communications Card
| dc.contributor.advisor | Redford, Gary | |
| dc.contributor.author | Brunton, Edward | |
| dc.creator | Brunton, Edward | |
| dc.date.accessioned | 2019-06-13T03:50:00Z | |
| dc.date.available | 2019-06-13T03:50:00Z | |
| dc.date.issued | 2019 | |
| dc.identifier.citation | Brunton, Edward. (2019). Engineering Design Program: Engine Communications Card (Bachelor's thesis, University of Arizona, Tucson, USA). | |
| dc.identifier.uri | http://hdl.handle.net/10150/632672 | |
| dc.description.abstract | The “Honeywell Engine Communications Card” provides a common interface between a memory bus and several signals while providing several features. The inputs signals will be transmitted in parallel. The Engine Communications Card will transmit several protocols include CAN, ARINC 429, RS-485/422, MIL-STD-1553, and Ethernet. The Engine Communications Card will have a chassis resilient to vibrations and fluctuating temperature. The Engine Communications Card is modular so that one or more of the input signals may be missing without affecting the operation of the card. Additionally, the Engine Communications Card circuit design is such that if a protocol is removed at board printing time, the Integrated Circuit chip responsible for that protocol can be left off the board as a cost saving measure. During runtime, any number of protocols can be shut off without affecting the performance of the system. | |
| dc.language.iso | en | |
| dc.publisher | The University of Arizona. | |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | |
| dc.title | Engineering Design Program: Engine Communications Card | |
| dc.type | text | |
| dc.type | Electronic Thesis | |
| thesis.degree.grantor | University of Arizona | |
| thesis.degree.discipline | Honors College | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.name | B.S. | |
| refterms.dateFOA | 2019-06-13T03:50:00Z |
