APSK SYMBOL TIMING AND CARRIER PHASE SYNCHRONIZATION ON AN FPGA IN A C-BAND TELEMETRY RECEIVER

Abstract

This paper presents the implementation of a standard PLL-based timing and phase synchronization system on hardware usingan FPGA. The synchronization system is shown to successfully recover a 16-APSK signal despite off sets in phase and frequency between the transmitter and receiver local oscillators. Furthermore, it is shown that system performance, in terms of symbol times required to achieve lock, is comparable to double-precision floating point simulations despite using fixed point numbers with as few as 5 fractional bits for most computations.