Reliability of Memories Built From Unreliable Components Under Data-Dependent Gate Failures
AffiliationUniv Arizona, Dept Elect & Comp Engn
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CitationS. Brkic, P. Ivaniš and B. Vasić, "Reliability of Memories Built From Unreliable Components Under Data-Dependent Gate Failures," in IEEE Communications Letters, vol. 19, no. 12, pp. 2098-2101, Dec. 2015, doi: 10.1109/LCOMM.2015.2496266.
JournalIEEE COMMUNICATIONS LETTERS
RightsCopyright © IEEE.
Collection InformationThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at email@example.com.
AbstractIn this letter, we investigate fault-tolerance of memories built from unreliable cells. In order to increase the memory reliability, information is encoded by a low-density parity-check (LDPC) code, and then stored. The memory content is updated periodically by the bit-flipping decoder, built also from unreliable logic gates, whose failures are transient and data-dependent. Based on the expander property of Tanner graph of LDPC codes, we prove that the proposed memory architecture can tolerate a fixed fraction of component failures and consequently preserve all the stored information, if code length tends to infinity.
VersionFinal accepted manuscript
SponsorsSeventh Framework Programme of the European Union