An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes
Name:
An Information Theoretical ...
Size:
857.6Kb
Format:
PDF
Description:
Final Accepted Manuscript
Affiliation
Univ Arizona, Dept Elect & Comp EngnIssue Date
2007-11-12
Metadata
Show full item recordPublisher
IEEECitation
B. Vasic and S. K. Chilappagari, "An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2438-2446, Nov. 2007, doi: 10.1109/TCSI.2007.902611.Rights
Copyright © 2007 IEEE.Collection Information
This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.Abstract
In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.ISSN
1549-8328Version
Final accepted manuscriptae974a485f413a2113503eed53cd6c53
10.1109/tcsi.2007.902611