Show simple item record

dc.contributor.authorVasic, Bane
dc.contributor.authorChilappagari, S.K.
dc.date.accessioned2020-07-31T23:18:22Z
dc.date.available2020-07-31T23:18:22Z
dc.date.issued2007-11-12
dc.identifier.citationB. Vasic and S. K. Chilappagari, "An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2438-2446, Nov. 2007, doi: 10.1109/TCSI.2007.902611.en_US
dc.identifier.issn1549-8328
dc.identifier.doi10.1109/tcsi.2007.902611
dc.identifier.urihttp://hdl.handle.net/10150/641959
dc.description.abstractIn this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rightsCopyright © 2007 IEEE.en_US
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/
dc.titleAn Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codesen_US
dc.typeArticleen_US
dc.contributor.departmentUniv Arizona, Dept Elect & Comp Engnen_US
dc.identifier.journalIEEE Transactions on Circuits and Systems I: Regular Papersen_US
dc.description.collectioninformationThis item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.en_US
dc.eprint.versionFinal accepted manuscripten_US
dc.source.journaltitleIEEE Transactions on Circuits and Systems I: Regular Papers
dc.source.volume54
dc.source.issue11
dc.source.beginpage2438
dc.source.endpage2446
refterms.dateFOA2020-07-31T23:18:23Z


Files in this item

Thumbnail
Name:
An Information Theoretical ...
Size:
857.6Kb
Format:
PDF
Description:
Final Accepted Manuscript

This item appears in the following Collection(s)

Show simple item record