An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes
dc.contributor.author | Vasic, Bane | |
dc.contributor.author | Chilappagari, S.K. | |
dc.date.accessioned | 2020-07-31T23:18:22Z | |
dc.date.available | 2020-07-31T23:18:22Z | |
dc.date.issued | 2007-11-12 | |
dc.identifier.citation | B. Vasic and S. K. Chilappagari, "An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2438-2446, Nov. 2007, doi: 10.1109/TCSI.2007.902611. | en_US |
dc.identifier.issn | 1549-8328 | |
dc.identifier.doi | 10.1109/tcsi.2007.902611 | |
dc.identifier.uri | http://hdl.handle.net/10150/641959 | |
dc.description.abstract | In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.rights | Copyright © 2007 IEEE. | en_US |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | |
dc.title | An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes | en_US |
dc.type | Article | en_US |
dc.contributor.department | Univ Arizona, Dept Elect & Comp Engn | en_US |
dc.identifier.journal | IEEE Transactions on Circuits and Systems I: Regular Papers | en_US |
dc.description.collectioninformation | This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu. | en_US |
dc.eprint.version | Final accepted manuscript | en_US |
dc.source.journaltitle | IEEE Transactions on Circuits and Systems I: Regular Papers | |
dc.source.volume | 54 | |
dc.source.issue | 11 | |
dc.source.beginpage | 2438 | |
dc.source.endpage | 2446 | |
refterms.dateFOA | 2020-07-31T23:18:23Z |