Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis
AffiliationUniv Arizona, Dept Elect & Comp Engn
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CitationF. Cai, X. Zhang, D. Declercq, S. K. Planjery and B. Vasić, "Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 5, pp. 1366-1375, May 2014, doi: 10.1109/TCSI.2014.2309896.
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AbstractLow-density parity-check (LDPC) codes are adopted in many applications due to their Shannon-limit approaching error-correcting performance. Nevertheless, belief-propagation (BP) based decoding of these codes suffers from the error-floor problem, i.e., an abrupt change in the slope of the error-rate curve that occurs at very low error rates. Recently, a new type of decoders termed finite alphabet iterative decoders (FAIDs) were introduced. The FAIDs use simple Boolean maps for variable node processing, and can surpass the BP-based decoders in the error floor region with very short word length. We restrict the scope of this paper to regular d v =3 LDPC codes on the BSC channel. This paper develops a low-complexity implementation architecture for the FAIDs by making use of their properties. Particularly, an innovative bit-serial check node unit is designed for the FAIDs, and a small-area variable node unit is proposed by exploiting the symmetry in the Boolean maps. Moreover, an optimized data scheduling scheme is proposed to increase the hardware utilization efficiency. From synthesis results, the proposed FAID implementation needs only 52% area to reach the same throughput as one of the most efficient standard Min-Sum decoders for an example (7807, 7177) LDPC code, while achieving better error-correcting performance in the error-floor region. Compared to an offset Min-Sum decoder with longer word length, the proposed design can achieve higher throughput with 45% area, and still leads to possible performance improvement in the error-floor region.
VersionFinal accepted manuscript