Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations
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Information Theoretic Modeling ...
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Final Accepted Manuscript
Affiliation
Univ Arizona, Dept Elect & Comp EngnIssue Date
2011-12-11
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S. Z. Denic, B. Vasic, C. D. Charalambous, J. Chen and J. M. Wang, "Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, pp. 397-410, March 2011, doi: 10.1109/TVLSI.2009.2033933.Rights
Copyright © 2009 IEEE.Collection Information
This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.Abstract
As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process variations cause errors in data delivering through interconnects. This paper proposes an Information Theory based design method to accommodate process variations. Different from the traditional delay based design metric, the current approach uses achievable rate to relate interconnect designs directly to communication applications. More specifically, the data communication over a typical interconnect, a bus, subject to process variations (“uncertain” bus), is defined as a communication problem under uncertainty. A data rate, called the achievable rate, is computed for such a bus, which represents the lower bound on the maximal data rate attainable over the bus. When a data rate applied over the bus is smaller than the achievable data rate, a reliable communication can be guaranteed regardless of process variations, i.e., a bit error rate arbitrarily close to zero is achievable. A single communication strategy to combat the process variations is proposed whose code rate is equal to the computed achievable rate. The simulations show that the variations in the interconnect resistivity could have the most harmful effect regarding the achievable rate reduction. Also, the simulations illustrate the importance of taking into account bus parasitic parameters correlations when measuring the influence of the process variations on the achievable rates.ISSN
1063-8210Version
Final accepted manuscriptae974a485f413a2113503eed53cd6c53
10.1109/tvlsi.2009.2033933