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dc.contributor.advisorShadman, Farhang
dc.contributor.authorStuffle, Calliandra
dc.creatorStuffle, Calliandra
dc.date.accessioned2022-08-18T22:51:23Z
dc.date.available2022-08-18T22:51:23Z
dc.date.issued2022
dc.identifier.citationStuffle, Calliandra. (2022). Etching and Cleaning of High-Aspect Ratio Features in MEMS and Semiconductor Device Manufacturing (Doctoral dissertation, University of Arizona, Tucson, USA).
dc.identifier.urihttp://hdl.handle.net/10150/665638
dc.description.abstractThe research in this dissertation focused on facets of the challenges of etching, cleaning, and rinsing of the high-aspect ratio features found in micro-electromechanical systems (MEMS) and semiconductor devices. The main goal of this work was to create a set of adaptable tools that can be used for predictive end pointing in wet chemical processing and as the foundation for automated process control. These tools can help to mitigate the environmental impact of currently resource intensive industrial practices, a key challenge for semiconductor processing.In the first study, an adaptable process simulator for studying the contaminant concentration evolution within high-aspect ratio features during wet chemical processing was developed and used to investigate the process end point. The process simulator was also used for a novel application: to study substrate undercut. Undercut is a key challenge associated with wet chemical cleaning and rinsing processes which occurs at the interface of two materials due to the attack and removal of an etch susceptible substrate. Two geometry systems were investigated to extend the number of applications for the simulator and to provide insight into pertinent feature architecture; a rectangular system which models commonly used trench architecture and a cylindrical system which models via architecture were both studied. The bottom “corner,” or intersection of the sidewall and the feature bottom, was identified as the bottleneck cleaning location for the HAR feature in each geometry system. The time it takes to lower the contaminant concentration at the bottleneck cleaning location to an established threshold was defined as the clean up time or process end point. The effect of several industrially relevant process parameters and variations in the feature size on the clean up time was studied, which also helped to illustrate the flexibility of the process simulator. When the concentration of the active cleaning species was increased in the bulk fluid, and when the mass transfer coefficient between the bulk fluid and that within the feature was increased, the cleanup time decreased due to the greater availability of the reactant. Both the feature size and feature aspect ratio were shown to influence the clean up time; the clean up time decreased with decreasing aspect ratio and the smaller feature in a pair of features with the same aspect ratio was found to have a shorter clean up time. Features with sidewalls formed from stacked substrate layers were studied in order to investigate information on undercut. Similar trends for the onset of undercut were observed with variations in the bulk fluid concentration, mass transfer coefficient, and feature shape as were for the cleanup time. Additionally, the location of the interface was shown to influence the onset of undercut for both feature geometries and the clean up time for the rectangular feature. The breadth of this study serves to show the flexibility of the process simulator to system definitions and processing conditions. The next study focused on adapting the generic process simulator to a specific and industrially relevant scenario. Silicon etch in highly alkaline conditions was the example studied as this is a frequent and important process in the silicon dominated industry of semiconductor manufacturing. A scenario where silicon dioxide is atop a silicon substrate and a shallow etch into the silicon will be deepened to create a trench in the silicon through wet chemical etching was studied. Silicon dioxide has a negligible etch rate in alkaline solutions while silicon exhibits plane dependent etch rates; the silicon is etched to a trench shape and the silicon dioxide mask remains in place. Kinetic parameters and important processing conditions including the reactant concentration and operating temperature were derived from the available data in the literature. Etch results for the silicon planes investigated were well matched to available literature values from other research groups and were consistent with expectations. The effect of the mass transfer coefficient and feature shape on the time required to double the depth of the feature into the silicon substrate was studied. Due to the relatively shallow shape of the feature at the beginning of the process, there was a relatively small effect on the etch time with changes in the mass transfer coefficient, which indicates the process is robust to small deviations in processing conditions like the rotation rate of the wafer and the flow rate of the highly alkaline solution which impact the mass transfer coefficient. The etch time more than doubled when the initial depth of the silicon feature was doubled, which indicates that the process should be carefully controlled when creating features of critical dimensions. Additionally, a feature with a silicon – silicon dioxide – silicon stack forming the sidewall was simulated. This novel setup was investigated to demonstrate the utility of the process simulator with complicated integration schemes that are becoming more relevant at advanced integrated circuit technology nodes. The final study focused on an application of the process simulator to scenarios with angled sidewall etching which occurs in part due to deviations in etch rates between different planes. This portion of the study built on the formulation used in the silicon etch scenario. However, an effective etch rate coefficient with vector components which consider both lateral and vertical etch rates was formulated to describe the effect of the angled sidewall formation. A parameter, Φ, was introduced to describe the angle of the sidewall; at higher values, the sidewall has a more aggressive slope. The effect of the mass transfer coefficient on Φ was investigated and the results indicated that Φ decreases with increasing mass transfer coefficient. However, the tradeoff is small at high values of the mass transfer coefficient. The results also indicate that the angle of the sidewall formed will not be sensitive to small deviations in processing conditions such as the rotation rate of the wafer at moderate values of the mass transfer coefficient. These results demonstrate the adaptability of the process simulator suite developed and how the results can be interpreted to help identify optimized processing conditions for desired feature profiles.
dc.language.isoen
dc.publisherThe University of Arizona.
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction, presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/
dc.subjectclean
dc.subjectetch
dc.subjectmicro-electrical mechanical systems
dc.subjectrinse
dc.subjectsemiconductor
dc.titleEtching and Cleaning of High-Aspect Ratio Features in MEMS and Semiconductor Device Manufacturing
dc.typetext
dc.typeElectronic Dissertation
thesis.degree.grantorUniversity of Arizona
thesis.degree.leveldoctoral
dc.contributor.committeememberOgden, Kimberly
dc.contributor.committeememberGuzman, Roberto
thesis.degree.disciplineGraduate College
thesis.degree.disciplineChemical Engineering
thesis.degree.namePh.D.
refterms.dateFOA2022-08-18T22:51:23Z


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