STT-RAM-Based Domain-Specific Architectures for Resource-Constrained Systems

Abstract

Resource-constrained consumer devices such as embedded systems, wearables, smartphones, etc., have become some of the fastest-growing products. Unlike general-purpose systems, resource-constrained devices are expected to perform various tasks within stringent area and energy constraints. Despite these stringent design constraints, resource-constrained devices are increasingly processing complex workloads due to increasing consumer demand. To meet these computational demands, resource-constrained devices must feature computational resources that satisfy the workloads' requirements without introducing substantial overhead. Domain-specific architectures (DSA) provide a happy medium between the efficiency of application-specific ICs (ASICs) and the flexibility of general-purpose architectures in wearable computing systems. Unlike general-purpose architectures, which are typically optimized for average case performance, domain-specific architectures are specialized with computational resources to optimize a particular domain of applications with similar execution characteristics. Compared to ASICs, DSAs substantially improve utilization while enabling performance and energy benefits for various applications. This dissertation explores Spin-transfer torque random access memory (STT-RAM) based domain-specific architectures for resource-constrained systems. STT-RAMs require low power and are much denser than SRAMs, making them a compelling alternative to SRAMs in resource-constrained systems. In this dissertation, we first analyze a set of resource-constrained workloads to study their workload characteristics and then propose domain-specific architectures design schemes and STT-RAM cache configurations to optimize them. Furthermore, to reduce the data movement in resource-constrained systems, we explored STT-RAM-based processing-in-cache (PiC) and processing-in-memory (PiM) computing, where the compute units are bought closer to the STT-RAM memory. In this dissertation, we discuss the trends in workload characteristics of resource-constrained systems and explore which memory hierarchy will benefit from PiM and PiC computations. Moreover, to compute multiple complex operations such as (shift, compare, multiply, etc.) without incurring high area and memory access overheads in PiC/PiM computing, we introduced a novel computing approach called Concurrent Hierarchical In-Memory Processing (CHIME), which incorporates distinct compute units at different levels of the memory hierarchy. We explore various design-space exploration strategies-- such as creating compute groups comprising multiple compute units and mapping them to the optimal level of the memory hierarchy. We performed detailed experiments to evaluate and quantify the extensive benefits ofthe work proposed herein. Results reveal that the proposed DSA, PiM/PiM design approaches, STT-RAM cache, and memory hierarchy can lead to highly energy-efficient and low-overhead solutions for emerging resource-constrained computer systems.